1. Field of the Invention
This invention relates to ferroelectric memories, and more particularly to such a memory utilizing such ferroelectric field effect transistors and methods of operating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950""s that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., xe2x80x9cThe Physics of Ferroelectric Memoriesxe2x80x9d, Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. However, it has been postulated for at least 40 years that it may be possible to design a memory in which the memory element is a ferroelectric field effect transistor (FeFET), which memory could be non-destructively read. See Shu-Yau Wu, xe2x80x9cA New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistorxe2x80x9d, IEEE Transactions On Electron Devices, pp. 499-504, Aug. 1974; S. Y. Wu, xe2x80x9cMemory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistorsxe2x80x9d, Ferroelectrics, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, xe2x80x9cIntegrated Ferroelectricsxe2x80x9d, Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long-lived two-state effect, it is now believed that this effect was charge injection effect rather than an effect due to ferroelectric switching.
To make a memory requires not only a memory element, but also a means for addressing a large number of memory elements. Initially, it was believed that a ferroelectric memory element might be addressed by a simple array of rows and columns of conductors. A ferroelectric memory element, it was thought, could be located at each of the junctures of the array and addressed by applying a voltage to the conductors for the corresponding row and column. It was believed that if the voltage on each conductor was less than the threshold voltage for ferroelectric switching (coercive voltage) and the voltage difference between the conductors was greater than the coercive voltage, then only the selected cell would be written to or read, and the other cells would remain unchanged. However, it was found that this did not work because the neighboring unselected cells were disturbed by the voltages on the address lines. Thus, a switch was added between one of the address lines and each ferroelectric memory element. See U.S. Pat. No. 2,876,436 issued Mar. 3, 1959 to J. R. Anderson and U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. If the switch is a transistor as in the latter patent, the memory assumes a memory address architecture essentially the same as that of a conventional DRAM. However, when applied to a ferroelectric memory, even this architecture disturbed the memory cells attached to the same plate line as the addressed cell. That is, it has been found that ferroelectric materials do not have a sharp coercive threshold voltage, but rather even a small voltage will cause the ferroelectric to partially switch and, therefore, the repetitive application of small disturb voltages, such as occur in a conventional memory array, eventually causes the change or loss of a memory state. Therefore, a more complex architecture was proposed to overcome this disturb. See, for example, U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley.
The above address schemes are all for a NVFRAM; that is, a memory utilizing a ferroelectric capacitor as a memory element, rather than for a memory utilizing an FeFET. A number of address architectures have been disclosed up to now for a memory in which the memory element is an FeFET.
A proposed solution to avoid the disturb problem in memories utilizing ferroelectrics is disclosed in U.S. Pat. No. 5,345,414 issued to Takashi Nakamura on Sep. 6, 1994. This solution utilizes three transistors in each memory cell: in one embodiment, the FeFET, a Metal Oxide Semiconductor field effect transistor (MOSFET) and a Metal Oxide Semiconductor Thin Film Transistor (MOSTFT); in other embodiments the FeFET and two MOSFETS in each cell. This solution is more complex than a DRAM or NVFRAM, not only because it has three electronic elements per cell, but also because in the embodiment with the MOSTFT, it requires a dual power supply, one to supply a positive voltage and one to supply a negative voltage. In the other embodiments, a dual power supply is not needed, but the erase voltage requires a voltage significantly higher than the supply voltage, and in the other, a forward bias between a positively charged substrate and the source is created in the erase function, which results in very high current flow for this function. In addition, two word lines are required in all the embodiments, which adds significant complexity to the architecture. U.S. Pat. No. 5,523,964 issued Jun. 4, 1996 to McMillan et al. discloses a relatively complex addressing architecture, utilizing five transistors in each memory cell in addition to the ferroelectric FET. This complexity is incorporated, like the Mobley et al. architecture, to avoid the disturb problem. All of the foregoing architectures result in a memory that is much less dense and slower than, for example, a conventional DRAM. An architecture that uses one ferroelectric FET per memory cell has been proposed, but has not been implemented because it cannot be read properly if three neighboring cells all are in the conducting logic state. See U.S. Pat. No. 5,449,935 issued to Takashi Nakamura on Sep. 12, 1995, col. 3, line 56-col. 4, line 15. Another such one-FET-per-memory cell design has been proposed in U.S. Pat. No. 5,768,185 issued to Takashi Nakamura and Yuichi Nakao on Jun. 16, 1998. However, during reading, a voltage of 3 volts to 5 volts is applied to the word line while the ground or zero volts is applied to the bit line. While this is not enough to switch the ferroelectric in a single read cycle, as indicated above, it is now known that successive pulses of this magnitude, such as occur in a memory in the normal process of reading, can disturb the ferroelectric state. In addition, since the bit line is connected to the source and substrate and the word line is connected to the gate, if the WLn and BLm+1 signals are not exactly synchronized, the erase process of one cell will disturb the next. Under manufacturing specifications that are practically feasible, such exact synchronization is difficult to achieve in all cells. Therefore, in a commercial product there will be short disturb voltages during the erase cycle also. Further, with this architecture, it is not possible to write a byte at a time, which is a much faster way of reading in a ferroelectric FET.
Thus, the fact that the ferroelectric material does not have a sharp coercive field threshold and can be switched by repetitive applications of a small voltage has made several of the original objectives of research into ferroelectric memories unattainable. In fact, at this writing, for the above reasons, no actual memory based on an FeFET has yet been made. It would, therefore, be highly desirable to provide an architecture and method for addressing a ferroelectric memory, particularly a ferroelectric FET structure and method of making the structure, that was relatively simple and, at the same time, avoided the problems in the prior art, such as the disturb problem.
The invention solves the above problem by providing ferroelectric memory in which each memory cell preferably contains only two electronic elements, a ferroelectric FET (FeFET) and a switching device, which is preferably a conventional transistor, such as a MOSFET. We shall refer to this cell herein as a 1T/1T memory cell. It is understood that other components can be added to the memory cell that do not essentially change its function as described herein.
The switching device within the cell is preferably operated in the erase and write functions to permit a gate voltage to be applied to the FeFET. When the switching device is a transistor, the transistor gate is coupled to a word line, and its source/drains are connected between a gate line and the FeFET gate.
In the erase function, an erase voltage of Vcc is placed on the substrate of the selected cell, and a zero voltage is placed on the gate line of the selected cell. In the write function, a write voltage of Vcc is placed on the gate line of the selected cell and a zero voltage is placed on the substrate.
As can be seen from the above operation, in distinction from the prior art, only a single power supply is required for this architecture, because all the voltages applied during the erase and write function are of one sign and are not higher than Vcc.
The invention also preferably includes a read switching device, which is also preferably a conventional transistor, such as a MOSFET. The read switching device is not part of the memory cell, and preferably is located in the peripheral circuitry. There is preferably one read switch for each row of cells, and it is operated to connect the one source/drain of the FeFETs in a selected row of cells to a current source during the read function. A current or voltage electronic state of a selected cell is preferably sensed via a bit line connected to the other source/drain of the selected FeFET to determine the logic state of the cell. The voltage of the current source is small, i.e., one volt or less, and preferably only about half a volt.
Preferably, during the erase function, a voltage of Vcc is also placed on the source/drain of the selected cell via the bit line to prevent a forward bias from developing at the substrate-source/drain interface.
Either byte or block erase may be used in operating the memory according to the invention. If block erase is used, there is less than one chance in 1011 of causing a disturb to a memory cell. Thus, this is the first ferroelectric memory architecture in which there is, in practice, no chance of a disturb happening.
(A summary of the claims will be inserted here after the claims are in final form)
The invention not only provides a simpler and much more dense ferroelectric memory in which the data in cells not being addressed are not disturbed when an addressed cell is written to or read, but also provides one that can be manufactured with state-of-the-art ferroelectric manufacturing processes. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.